Probabilistic Testability Analysis and DFT Methods at RTL

Abstract

This work presents probabilistic methods for testability analysis at RTL and their use to guide DFT techniques like partial-scan and TPI. Controllability is analyzed using an approach that takes into account correlations within pre-defined groups formed based on an originally proposed heuristic. A method for observability computation at RTL based on the Boolean difference is presented. These testability analysis methods were implemented in a tool that reads a Verilog RTL description, solves the Chapman-Kolmogorov equations that describe the steady-state of the circuit, and outputs the computed values for the testability. A methodology for partial-scan and TPI optimization is proposed and implemented. The methodology is based on the testability metrics and on a "DFT dictionary". The proposed heuristic and methodology are evaluated using the ITC99 benchmark circuits