DFT and Probabilistic Testability Analysis at RTL

Abstract

This work presents probabilistic methods for testability analysis at RTL and their use to guide DFT techniques like partial-scan and TPI. Controllability is analyzed using three different approaches, an exact one, an approximated one that ignores the correlation between state variables and a third that only takes into account correlations within pre-defined groups that are formed based on an originally proposed heuristic that uses RTL information. These controllability analysis methods are evaluated using simulation based controllability as a reference. Two observability metrics are originally defined: event observability and LSA observability. The proposed testability analysis methods were implemented in a tool that takes as input a Verilog RTL description, solves the Chapman-Kolmogorov equations that describe the steady-state of the circuit, and outputs the computed values for the testability. A methodology for partial-scan and TPI optimization is proposed. The methodology is based on the testability metrics and on a "DFT dictionary". The proposed heuristic and methodology are evaluated using the ITC99 benchmark circuits